Dynamic random-access memory (dram) device, memory bank of dram device and method thereof

A dynamic random-access memory (DRAM) device, comprising:

• a plurality of memory cells, comprising first selected memory cells and second selected memory cells for a memory operation;
• a plurality of bit line pairs, comprising first-bank bit line pairs and second-bank bit line pairs, wherein the first-bank bit line pairs are connected to the first selected memory cells, and the second-bank bit line pairs are connected to the second selected memory cells;
• a plurality of switch pairs, comprising first-bank switch pairs and second-bank switch pairs, wherein the first-bank switch pairs are connected to the first-bank bit line pairs and the second-bank switch pairs are connected to the second-bank bit line pairs;
• and
• a plurality of sense amplifiers, connected to the bit line pairs via the switch pairs, each sense amplifier being connected to at least two bit line pairs via at least two switch pairs,
• wherein the first-bank switch pairs are configured to electrically connect the sense amplifiers to the first-bank bit line pairs during a first row cycle time period, and the sense amplifiers are configured to perform the memory operation on the first selected memory cells connected to the first-bank bit line pairs during the first row cycle time period, and
• the second-bank switch pairs are configured to electrically connect the sense amplifiers to the second-bank bit line pairs during a second row cycle time period, and the sense amplifiers are configured to perform the memory operation on the second selected memory cells connected to the second-bank bit line pairs during the second row cycle time period.

A method of a dynamic random-access memory (DRAM) device comprising a first physical memory area corresponding to a first memory mat, and a second physical memory area corresponding to a second memory mat, a plurality of sense amplifiers, a plurality of bit line pairs and a plurality of switch pairs, the method comprising:

• selecting a plurality of memory cells for a memory operation, wherein the memory cells comprise memory cells of a first memory bank and memory cells of a second memory bank, and the memory cells of the first memory bank and the memory cells of the second memory bank are arranged alternately in each of the first physical memory area and the second physical memory area;
• controlling switch pairs of the first memory bank to electrically connect the sense amplifiers to the first-bank bit line pairs in the first physical memory area and the second physical memory area during a first row cycle time period;
• and
• performing a memory operation to the memory cells connected to the first-bank bit line pairs in the first physical memory area and the second physical memory area during the first row cycle time period.