Memory device including ferroelectric cell capacitor and operating method thereof

An operating method of a memory device, the method comprising:

• during a first time period in a read operation, applying a ground voltage to a first plate line connected to a first memory cell and a second plate line connected to a second memory cell;
• in the first time period, applying the ground voltage to a bit line commonly connected to the first memory cell and the second memory cell;
• during a second time period in the read operation, reading data stored in one of the first memory cell and the second memory cell by performing a charge sharing operation;
• during a third time period in the read operation, applying a first plate line driving voltage to a plate line corresponding to a memory cell storing first data among the first and second memory cells;
• and
• in the third time period, applying a second plate line driving voltage to a plate line corresponding to a memory cell storing second data among the first and second memory cells.

A memory device comprising:

• a memory cell array comprising a first layer comprising a plurality of first memory cells and a second layer comprising a plurality of second memory cells;
• a first plate line decoder connected to the first layer;
• a second plate line decoder connected to the second layer;
• a common bit line connected to the first layer and the second layer;
• and
• a word line decoder connected to the first layer and the second layer,
• wherein, during a write operation on the memory cell array, a voltage applied to the common bit line is maintained at a ground voltage.