US 2025/0157508 A1 · MEMORY DEVICE AND COMPUTATION METHOD THEREOF

Abstract

The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.

Claims10

Dependent claims

A computational method for a memory device, comprising:

storing a plurality of weight data in a plurality of first memory cells of the memory device;
inputting a plurality of input data via a plurality of first string select lines;
generating a plurality of memory cell currents in the plurality of first memory cells based on the weight data and the input data;
summing the memory cell currents on a plurality of bit lines coupled to the plurality of first string select lines to obtain a plurality of summed currents;
converting the summed currents into a plurality of analog-to-digital conversion results;
and
accumulating the plurality of analog-to-digital conversion results to obtain a computational result.

4 more elements

A memory device comprising:

a plurality of first memory cells storing a plurality of weight data;
a plurality of first string select lines coupled to the plurality of first memory cells;
a plurality of bit lines coupled to the plurality of first string select lines;
a plurality of converters coupled to the plurality of bit lines;
and
an accumulator coupled to the plurality of converters,
wherein
the plurality of input data are inputted via the plurality of first string select lines;
a plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data;
the memory cell currents are summed on the plurality of bit lines to obtain a plurality of summed currents;
the converters convert the plurality of summed currents into a plurality of analog-to-digital conversion results;
and
the accumulator accumulates the plurality of analog-to-digital conversion results to obtain a computational result.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/641,578Filed 22 Apr 2024

Priority

14 Nov 2023

Published

15 May 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 7/1096
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: write circuits, e.g.…
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/16
Arrangements for writing information into, or reading information out from, a digital store: storage of analogue signals in digital stores using…

Memory device and computation method thereof

Life of this patent

Memory device and computation method thereof

Life of this patent

Abstract

Claims10