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US 2025/0157503 A1Published application
Memory with deferred fractional row activation
AssigneeRambus Inc.
InventorsJames E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
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Abstract
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
Claims21
1-20. (canceled)
A method of operation within a memory control component, the method comprising:
- outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component;
- and
- after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to:
- transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
- and
- charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
3 more elements
A memory control component comprising:
- a first signaling interface;
- and
- control circuitry to output via the first signaling interface:
- a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component;
- and
- a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to:
- transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
- and
- charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
6 more elements
A memory control component comprising:
- a first signaling interface;
- and
- means for outputting via the first signaling interface:
- a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component;
- and
- a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to:
- transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
- and
- charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
6 more elements
Dependencies are inferred from the claim text.