Gate driver unit and display panel

A display panel, comprising:

• a gate driver unit comprising a plurality of gate driver circuits, at least one of the gate driver circuits each comprising a first node control module, a first output module, an output control module, and a second output module;
• wherein the first node control module is electrically connected to a first node of the gate driver circuit at a present stage and a second node of the gate driver circuit at the present stage, and the first node control module is configured to transmit a first power supply signal to the first node according to a potential of the second node and a corresponding first clock signal, or transmit a second power supply signal to the first node according to the potential of the second node;
• the first output module is electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and the first output module is configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node;
• the output control module is electrically connected to the first node of the gate driver circuit at the present stage and to a third node of the gate driver circuit at the present stage, and the output control module is configured to electrically connect the first node and the third node or to disconnect an electrical connection between the first node and the third node;
• the second output module is electrically connected to the second node, the third node, and a second output terminal of the gate driver circuit at the present stage, the second output module is configured to output a corresponding second clock signal or the first power supply signal to the second output terminal according to the potential of the second node and a potential of the third node, and wherein at least one of the first node control module and the output control module is electrically connected to the second node of the gate driver circuit at a preceding stage;
• and
• a plurality of sub-pixels, at least one of the sub-pixels each comprising a light emitting device and a pixel driver circuit for driving the light emitting device to emit light, the pixel driver circuit comprising a driving transistor, a compensation transistor and a data transistor, an input terminal and an output terminal of the compensation transistor being electrically connected between a control terminal and an output terminal of the driving transistor, an input terminal of the data transistor being configured to receive a corresponding data signal, and an output terminal of the data transistor being electrically connected to the input terminal of the driving transistor;
• and
• wherein the first output terminals of the plurality of gate driver circuits are electrically connected to the control terminals of the compensation transistors of the plurality of sub-pixels, and the second output terminals of the plurality of gate driver circuits are electrically connected to the control terminals of the data transistors of the plurality of sub-pixels.