Circuit layout verification method and system

A circuit layout verification system, comprising:

• a storage unit configured to store an instruction set and a circuit layout;
• and
• a processor coupled to the storage unit, the processor configured to read the instruction set to perform the following operations:
• reading a circuit layout;
• setting parameters for components in the circuit layout, based on that:
• a voltage difference between a first electrode and a third electrode of a transistor in the circuit layout is equivalent to a transistor voltage drop,
• a resistor in the circuit layout is considered as a short circuit, and
• a voltage difference between an anode and a cathode of a diode in the circuit layout is equivalent to a diode voltage drop;
• according to a preset voltage value of at least one port in the circuit layout, performing a direct current (DC) analysis on the circuit layout after the setting is performed to calculate a maximum possible voltage value and a minimum possible voltage value of a wire segment in the circuit layout;
• and
• inputting the maximum possible voltage value and the minimum possible voltage value into a predetermined design specification, wherein when the maximum possible voltage value or the minimum possible voltage value exceeds the predetermined design specification, the wire segment is marked as abnormal.