Memory module with computation capability
AssigneeMicron Technology, Inc.
InventorDmitri Yudanov
Life of this patent
Estimating the term…
Abstract
A memory module having a plurality of memory chips, at least one controller (e.g., a central processing unit or special-purpose controller), and at least one interface device configured to communicate input and output data for the memory module. The input and output data bypasses at least one processor (e.g., a central processing unit) of a computing device in which the memory module is installed. And, the at least one interface device can be configured to communicate the input and output data to at least one other memory module in the computing device. Also, the memory module can be one module in a plurality of memory modules of a memory module system.
Claims20
A memory device, comprising:
- at least one interface device configured to:
- communicate data for the memory device such that the data is configured to bypass at least one external processor of a computing device;
- and
- at least one arbiter configured to:
- arbitrate access to the data when at least one controller of the memory device and the at least one external processor of the computing device attempt to access the data.
A system, comprising:
- a memory module, comprising:
- at least one interface device configured to:
- provide data for the memory module such that the data is configured to bypass a first data bus in communication with the memory module;
- and
- at least one arbiter configured to:
- control access to the data when at least one controller of the memory module and at least one processor external to the memory module attempt to access the data.
A method, comprising:
- communicating, by utilizing at least one interface device of a memory device, data for the memory device such that the data is configured to bypass at least one external processor;
- and:
- arbitrating, by utilizing at least one arbitrator of the memory device, access to the data when at least one controller of the memory device and the at least one external processor attempt to access the data.
Dependencies are inferred from the claim text.