Hardware acceleration circuit, data processing acceleration method, chip, and accelerator

Abstract

A hardware acceleration circuit, a data processing acceleration method, a chip, and an accelerator are provided. The circuit includes: an exponential function module, configured to obtain a plurality of exponential function values of a plurality of data elements in a data set; an add-subtract module, configured to obtain an addition operation result of the exponential function values; and a natural logarithm function module, configured to obtain a natural logarithm value of the addition operation result, where the add-subtract module is further configured to obtain a subtraction operation result of an ith data element in the data elements and the natural logarithm value; and the exponential function module is further configured to obtain an exponential function value of the subtraction operation result, to obtain a specific function value corresponding to the ith data element. Solutions provided in embodiments of this application facilitate an increase in precision of a non-linear function value.

Dependencies are inferred from the claim text.