Floating point division using variable length integer division
AssigneeSkyworks Solutions, Inc.
InventorMikael Mortensen
Life of this patent
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Abstract
A division circuit including a first normalizer configured to shift a first input to a first higher power; a second normalizer configured to shift a second input to a second higher power; a subtraction circuit configured to iteratively subtract the second input from the first input for a number of iterations to produce a result, the number of iterations based on a number of shifts of the first input; a first output configured to provide the result; and a second output configured to provide the number of iterations.
Claims20
A division circuit comprising:
- a first normalizer configured to shift a first input to a first higher power;
- a second normalizer configured to shift a second input to a second higher power;
- a subtraction circuit configured to iteratively subtract the second input from the first input for a number of iterations to produce a result, the number of iterations based on a number of shifts of the first input;
- a first output configured to provide the result;
- and
- a second output configured to provide the number of iterations.
A computer system comprising:
- a division circuit;
- and
- at least one controller, the at least one controller configured to:
- provide an instruction to the division circuit to perform a division;
- receive, from the division circuit, a number of iterations corresponding to a number of clock cycles that the division will take to perform;
- execute one or more operations for the number of clock cycles while the division is being performed by the division circuit;
- and
- receive a result of the division.
A method for efficiently utilizing computational resources, the method comprising sequentially performing operations following a beginning of a division operation using computational resources other than the division circuit for a number of clock cycles equal to or greater than a minimum number of clock cycles, wherein the minimum number of clock cycles is determined by shifting a first input to a first higher power by a first number of shifts and modifying the first number of shifts by a second value to produce a number of iterations corresponding to the minimum number of clock cycles.
Dependencies are inferred from the claim text.