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US 2025/0155501 A1Published application
Chip and chip testing method
AssigneeRealtek Semiconductor Corp.
InventorsChang-Hsien Tai, Ren-Li Yang
Life of this patent
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Abstract
A chip testing method includes the following operations: during a chip probe testing, executing, by a processor circuit in a chip, a code to generate a first test signal; and during the chip probe testing, utilizing the first test signal to perform a transition delay fault test on a first circuit in the chip.
Claims20
A chip testing method, comprising:
- during a chip probe testing, executing, by a processor circuit in a chip, a code to generate a first test signal;
- and
- during the chip probe testing, utilizing the first test signal to perform a transition delay fault test on a first circuit in the chip.
A chip, comprising:
- a memory circuit configured to store a code;
- a processor circuit configured to execute the code during a chip probe testing to generate a first test signal;
- and
- a first circuit coupled to the processor circuit via a bus circuit and configured to perform a transition delay fault test in response to the first test signal during the chip probe testing.
1 more element
Dependencies are inferred from the claim text.