Dynamic latch, dynamic d flip-flop, data operation unit, chip, hash board, and computing device

A dynamic D flip-flop, comprising:

• an input terminal for inputting a first data;
• an output terminal for outputting a second data;
• a clock signal terminal for supplying a clock signal;
• a first latch for latching the first data under control of the clock signal;
• and
• a second latch for receiving and latching a data transmitted by the first latch,
• wherein the first latch and the second latch are sequentially connected in series between the input terminal and the output terminal, the first latch comprises a first data transmission unit and a first data output unit, the second latch comprises a second data transmission unit and a second data output unit, a first node is provided between the first data transmission unit and the first data output unit, and a second node is provided between the second data transmission unit and the second data output unit,
• the dynamic D flip-flop further comprises:
• a data retention unit electrically connected to the first node and/or the second node.