Semiconductor package

A semiconductor package, comprising:

• a package substrate including a package base insulating layer, a lower solder resist layer covering a lower surface of the package base insulating layer, and an upper solder resist layer covering an upper surface of the package base insulating layer;
• a plurality of semiconductor chips each including a substrate, a front protective layer disposed on a lower surface of the substrate, and a rear protective layer disposed on an upper surface of the substrate,
• wherein the plurality of semiconductor chips includes a first semiconductor chip disposed on the package substrate and a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip in a first direction;
• a plurality of first chip connection terminals disposed between the package substrate and the first semiconductor chip and electrically connecting the package substrate to the first semiconductor chip;
• a plurality of first chip support structures disposed between the package substrate and the first semiconductor chip,
• wherein the plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in a second direction and extend into the upper solder resist layer;
• a plurality of second chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips,
• wherein the plurality of second chip connection terminals electrically connect the two adjacent semiconductor chips, and the second direction crosses the first direction;
• and
• a plurality of second chip support structures disposed between the two adjacent semiconductor chips,
• wherein the plurality of second chip support structures extend into the rear protective layer included in a lower semiconductor chip among the two adjacent semiconductor chips.

A semiconductor package, comprising:

• a package substrate including a package base insulating layer, a plurality of package upper pads disposed on an upper surface of the package base insulating layer, a plurality of package lower pads disposed on a lower surface of the package base insulating layer, a plurality of connection pads electrically connecting the plurality of package upper pads to the plurality of package lower pads, an upper solder resist layer covering the upper surface of the package base insulating layer and not covering at least a portion of an upper surface of each of the plurality of package upper pads, and a lower solder resist layer covering the lower surface of the package base insulating layer and not covering at least a portion of a lower surface of each of the plurality of package lower pads;
• a plurality of semiconductor chips including a first semiconductor chip and a plurality of second semiconductor chips sequentially stacked on the package substrate in a first direction,
• wherein the first semiconductor chip and the plurality of second semiconductor chips each include a substrate, a plurality of rear connection pads disposed on an upper surface of the substrate, a plurality of front connection pads disposed on a lower surface of the substrate, a plurality of through-electrodes vertically penetrating through at least a portion of the substrate and electrically connecting the plurality of rear connection pads to the plurality of front connection pads, a front protective layer disposed on the lower surface of the substrate and not covering at least a portion of a lower surface of each of the plurality of front connection pads, and a rear protective layer disposed on the upper surface of the substrate and not covering at least a portion of an upper surface of each of the plurality of rear connection pads;
• a plurality of first chip connection terminals disposed between the plurality of package upper pads of the package substrate and the plurality of front connection pads of the first semiconductor chip;
• a plurality of first chip support structures disposed between the package substrate and the first semiconductor chip,
• wherein the plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in a second direction, extend into the upper solder resist layer, and do not penetrate through the upper solder resist layer;
• a plurality of second chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips and disposed between the plurality of rear connection pads and the plurality of front connection pads facing each other included in the two adjacent semiconductor chips,
• wherein the second direction crosses the first direction;
• and
• a plurality of second chip support structures disposed between the two adjacent semiconductor chips,
• wherein the plurality of second chip support structures extend into the rear protective layer included in a lower semiconductor chip among the two adjacent semiconductor chips and do not penetrate through the rear protective layer.