Semiconductor package

A semiconductor package comprising:

• a buffer die;
• memory dies sequentially stacked on the buffer die;
• a conductive connection member between the memory dies, the conductive connection member including a first conductive pattern and a second conductive pattern stacked in a vertical direction substantially perpendicular to an upper surface of the buffer die, and the first and second conductive patterns including different materials from each other;
• a bonding layer between the memory dies, wherein the bonding layer is configured to bond ones of the memory dies with each other;
• and
• a molding member on the buffer die, wherein the molding member is on sidewalls of the memory dies,
• wherein each of the memory dies includes:
• a substrate having first and second surfaces opposite to each other in the vertical direction;
• and
• a signal pad and a test pad structure on the first surface of the substrate,
• wherein the test pad structure includes a test pad and a third conductive pattern stacked in the vertical direction on the first surface of the substrate,
• wherein the signal pad contacts the first conductive pattern of the conductive connection member, and
• wherein a distance from the substrate to a lowermost surface of the third conductive pattern is less than a distance from the substrate to a lower surface of the first conductive pattern.

A semiconductor package comprising:

• a first die;
• a second die on the first die;
• a conductive connection member between the first and second dies, the conductive connection member including first and second conductive patterns stacked in a vertical direction substantially perpendicular to an upper surface of the first die, and the first and second conductive patterns including different materials from each other;
• and
• a bonding layer between the first and second dies, wherein the bonding layer is configured to bond the first and second dies with each other and is on sidewalls of the conductive connection member,
• wherein the first die includes a first substrate having first and second surfaces opposite to each other in the vertical direction,
• wherein the second die includes:
• a second substrate having first and second surfaces opposite to each other in the vertical direction;
• and
• a signal pad and a test pad structure on the first surface of the second substrate,
• wherein the test pad structure includes a test pad and a third conductive pattern stacked in the vertical direction on the first surface of the second substrate,
• wherein the third conductive pattern has an uneven lower surface, and
• wherein the signal pad contacts the conductive connection member and the first conductive pattern, and
• wherein distance from the first substrate to a lowermost surface of the third conductive pattern is less than distance from the first substrate to a lower surface of the first conductive pattern.