Photonic assembly for enhanced bonding yield and methods for forming the same

A photonic assembly comprising:

• an electronic integrated circuits (EIC) die comprising a semiconductor substrate, a semiconductor lens which comprises a portion of the semiconductor substrate and has a convex semiconductor surface;
• semiconductor devices located on a surface of the semiconductor substrate, first dielectric material layers having first metal interconnect structures formed therein, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers and having an areal overlap with the semiconductor lens in a plan view;
• and a first bonding-level dielectric layer having first metal bonding pads formed therein, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in the plan view;
• and
• a photonic integrated circuits (PIC) die comprising waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer having second metal bonding pads formed therein, wherein the second metal bonding pads are bonded to the first metal bonding pads.

A method of forming a device structure, the method comprising:

• forming semiconductor devices on a horizontal surface of a semiconductor substrate;
• forming first metal interconnect structures within first dielectric material layers over the semiconductor devices;
• forming a via cavity through the first dielectric material layers such that a portion of the semiconductor substrate is exposed underneath the via cavity;
• forming a semiconductor lens by patterning the portion of the semiconductor substrate underneath the via cavity;
• forming a dielectric pillar structure by filling the via cavity with a dielectric fill material;
• forming a first bonding-level dielectric layer over the first dielectric material layers and the dielectric pillar structure;
• and
• forming first metal bonding pads in the first bonding-level dielectric layer, whereby an electronic integrated circuits (EIC) die is formed, and wherein a first subset of the first metal bonding pads is formed with an areal overlap with the dielectric pillar structure in a plan view.