Semiconductor package and method of fabricating the same

A semiconductor package comprising:

• a semiconductor substrate comprising a front side and a back side that is opposite to the front side;
• a semiconductor device layer on the front side of the semiconductor substrate;
• a chip wiring layer comprising:
• an inter-wiring insulating film, which covers the semiconductor device layer;
• and
• wiring structures within the inter-wiring insulating film and electrically connected to the semiconductor device layer;
• a front-side bonding layer comprising:
• a front-side bonding insulating film covering the chip wiring layer;
• and
• a front-side bonding pad within the front-side bonding insulating film and electrically connected to the wiring structures;
• a back-side bonding layer comprising:
• a back-side bonding insulating film on the back side of the semiconductor substrate;
• and
• a back-side bonding pad within the back-side bonding insulating film;
• and
• a through via penetrating the semiconductor substrate and the semiconductor device layer, and electrically connecting the front-side bonding pad and the back-side bonding pad,
• wherein a side of the semiconductor substrate comprises a plurality of first recesses arranged along a vertical direction that intersects the front side and the back side,
• wherein a side of the back-side bonding layer comprises a second recess between a top surface of the back-side bonding layer and the plurality of first recesses, and
• wherein a size of the second recess is greater than a size of each of the first recesses.

A semiconductor package comprising:

• a lower semiconductor chip;
• and
• a plurality of semiconductor chips sequentially provided on the lower semiconductor chip,
• wherein each of the plurality of semiconductor chips comprises:
• a semiconductor substrate comprising a front side facing the lower semiconductor chip, and a back side that is opposite to the front side;
• a semiconductor device layer on the front side of the semiconductor substrate;
• a chip wiring layer on the semiconductor device layer;
• a front-side bonding layer comprising:
• a front-side bonding insulating film on the chip wiring layer;
• and
• a front-side bonding pad within the front-side bonding insulating film;
• a back-side bonding layer comprising:
• a back-side bonding insulating film on the back side of the semiconductor substrate;
• and
• a back-side bonding pad within the back-side bonding insulating film;
• and
• a through via penetrating the semiconductor substrate and electrically
• connecting the front-side bonding pad and the back-side bonding pad, wherein a side of each of the plurality of semiconductor chips comprises:
• a plurality of first recesses arranged along a vertical direction that intersects the front side and the back side;
• and
• a second recess between a top surface of the back-side bonding layer and the plurality of first recesses, and
• wherein a size of the second recess is greater than a size of each of the first recesses.