Top die back-side marking for memory systems

A method, comprising:

• bonding a memory die with a carrier die, the memory die comprising a silicon layer and one or more pillars positioned on a first side of the silicon layer;
• identifying a first location of a first alignment mark on the first side of the silicon layer;
• forming one or more second alignment marks at a plurality of locations on a second side of the silicon layer based at least in part on identifying the first location of the first alignment mark, wherein the first alignment mark and the one or more second alignment marks are usable for aligning the memory die as a top die in a multi-layer semiconductor device;
• and
• debonding the memory die from the carrier die.

A method, comprising:

• aligning a first memory die with a second memory die, the first memory die comprising a first pillar positioned on a first side of a first silicon layer, a first pad positioned on a second side of the first silicon layer, and a first via extending through the first silicon layer and coupled with the first pillar and the first pad, the second memory die comprising a second pillar positioned on a first side of a second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die to contact the second pad of the second memory die;
• aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die positions the third pillar of the third memory die to contact the first pad of the first memory die based at least in part on the one or more marks on the second side of the third silicon layer;
• bonding the third memory die and the first memory die together to form a multi-layer semiconductor device;
• determining an alignment offset between the third memory die and the first memory die based at least in part on the one or more marks;
• and
• adjusting one or more alignment procedures for a second multi-layer semiconductor device based at least in part on the alignment offset.

An apparatus, comprising:

• a first memory die aligned with a second memory die, the first memory die comprising a first pillar positioned on a first side of a first silicon layer, a first pad positioned on a second side of the first silicon layer, and a first via extending through the first silicon layer and coupled with the first pillar and the first pad, the second memory die comprising a second pillar positioned on a first side of a second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein the first memory die has the first pillar of the first memory die in contact with the second pad of the second memory die;
• and
• a third memory die aligned with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein the third memory die has the third pillar of the third memory die in contact with the first pad of the first memory die based at least in part on the one or more marks on the second side of the third silicon layer;
• wherein the third memory die and the first memory die are bonded together to form a multi-layer semiconductor device.