Back to results
US 2025/0149459 A1Published application
Local density control for metal capacitance reduction
AssigneeIntel Corporation
InventorsBurak Baylav, Dhananjay Bhawe
Life of this patent
Estimating the term…
Abstract
An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.
Claims20
A method, comprising:
- receiving a design for an integrated circuit structure layout;
- cleaving each of a plurality of redundant metal lines in the integrated circuit structure layout to an active metal line and a preliminary dummy line;
- splitting the integrated circuit structure layout into regions and determining a line density in each of the regions;
- and
- segmenting at least one of the preliminary dummy lines to define a plurality of dummification lines within at least one of the regions.
2 more elements
A method, comprising:
- receiving a design for an integrated circuit structure layout;
- cleaving each of a plurality of redundant metal lines in the integrated circuit structure layout to an active metal line and a preliminary dummy line;
- grouping the plurality of preliminary dummy lines;
- splitting the integrated circuit structure layout into a plurality of regions and determining a line density in each of the plurality of regions;
- and
- altering lengths of and spaces between at least some of the preliminary dummy lines to form a plurality of dummification lines within a first region of the plurality of regions.
3 more elements
A method to control line density in an integrated circuit layout, comprising:
- inputting a design for an integrated circuit structure layout into a density calculation program;
- identifying and converting a plurality of redundant metal lines in the integrated circuit structure layout to a plurality of preliminary dummy lines;
- grouping the plurality of preliminary dummy lines;
- splitting the integrated circuit structure layout into regions and determining a line density in each of the regions;
- and
- calculating lengths of each of a plurality of dummification lines and spaces between the plurality of dummification lines within each region.
3 more elements
Dependencies are inferred from the claim text.