US 2025/0149453 A1 · SEMICONDUCTOR MEMORY DEVICE HAVING WORD LINES SURROUNDED BY MEMORY LAYERS AND METHOD OF MAKING THE SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes first and second memory units, and first and second staircase vias. The first memory unit includes two first source/bit line portions separated from each other, a first word line surrounding the first source/bit line portions, a first memory film surrounding the first word line, and a first channel region between the first memory film and the first source/bit line portions. The second memory unit is disposed over the first memory unit, and includes two second source/bit line portions separated from each other, a second word line surrounding the second source/bit line portions, a second memory film surrounding the second word line, and a second channel region between the second memory film and the second source/bit line portions. The first and second staircase vias respectively penetrate the first and second memory films, and are respectively and electrically connected to the first and second word lines.

Claims20

Dependent claims

A method of manufacturing a semiconductor memory device, comprising:

forming an etched stack structure over a semiconductor structure, the etched stack structure including first dielectric layers and second dielectric layers that are alternatingly stacked over the semiconductor structure, and the etched stack structure being formed with a main portion and a staircase portion connected to the main portion;
forming an inter-metal dielectric layer over the staircase portion;
forming channel segments and isolation segments in the main portion, wherein the isolation segments are surrounded by the channel segments, respectively;
forming conductive lines in the isolation segments;
forming memory segments respectively in place of the second dielectric layers and contacting the channel segments;
forming conductive segments in the memory segments, respectively;
and
forming conductive vias in the inter-metal dielectric layer, the conductive vias being electrically connected to the conductive segments, respectively, widths of the conductive vias increasing away from the main portion.

5 more elements

A method of manufacturing a semiconductor memory device, comprising:

forming a first stack segment and a second stack segment over a semiconductor structure in a first direction perpendicular to a substrate of the semiconductor structure, the first stack segment and the second stack segment being spaced apart from each other in a second direction perpendicular to the first direction and parallel to the substrate, each of the first stack segment and the second stack segment including first dielectric segments and second dielectric segments alternatingly stacked over the semiconductor structure in the first direction, and being formed with a main part and a staircase part extending from the main part in a third direction perpendicular to the first direction and the second direction;
forming an inter-metal dielectric segment over the staircase part;
forming channel segments in the main part of each of the first stack segment and the second stack segment along the first direction;
forming memory segments respectively in place of the second dielectric segments and contacting the channel segments;
forming conductive segments in the memory segments, respectively;
and
forming first conductive vias in the inter-metal dielectric segment, the first conductive vias being connected to conductive segments, respectively.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having word lines surrounded by memory layers and method of making the semiconductor memory device

Life of this patent

Semiconductor memory device having word lines surrounded by memory layers and method of making the semiconductor memory device

Life of this patent

Abstract

Claims20