New method to enable 30 microns pitch emib or below

A method of fabricating a semiconductor device, the method comprising:

• providing a first integrated circuit die, the first integrated circuit die having a first die interconnect structure and a second die interconnect structure;
• providing a second integrated circuit die adjacent and laterally spaced from the first integrated circuit die;
• coupling the first integrated circuit die and the second integrated circuit die to a substrate, the substrate having a substrate top side adjacent the first integrated circuit die and second integrated circuit die, and a substrate bottom side opposite the top side, wherein forming the substrate comprises:
• embedded bridge in the substrate, a first portion of the bridge being below a portion of the first integrated circuit die and a second portion of the bridge being below a portion of the second integrated circuit die, the bridge having a bridge top surface, a bridge bottom surface, the bridge top surface being closer to the first integrated circuit die than the bridge bottom surface is, and the bridge having a first bridge contact pad at the bridge top surface;
• forming a first bridge via connected to the first bridge contact pad, extending from the first bridge contact pad away from the bridge top surface, the first bridge via having a first bridge via height;
• forming a first bridge contact connected to the first bridge via, extending from a top of the first bridge via towards the first integrated circuit die, the first bridge contact having a first width, the first bridge contact being electrically coupled to the first die interconnect structure;
• forming a first non-bridge via laterally spaced from the embedded bridge, the first non-bridge via having a first non-bridge via height greater than the first bridge via height, wherein the first non-bridge via has a top surface above a top surface of the first bridge contact pad;
• forming a first conductive portion of a redistribution layer above and connected to the first non-bridge via;
• and
• forming a first non-bridge contact laterally spaced away from the bridge and above and connected to the first conductive portion of the redistribution layer, the first non-bridge contact positioned so that a line parallel to the bridge top surface intersects both the first bridge contact and the first non-bridge contact, the first non-bridge contact having a second width greater than the first width of the first bridge contact, the first non-bridge contact being electrically coupled to the second die interconnect structure.

A method of fabricating a computing device, the method comprising:

• providing a motherboard;
• coupling a first integrated circuit die electrically to the motherboard, the first integrated circuit die having a first die interconnect structure and a second die interconnect structure;
• providing a second integrated circuit die adjacent and laterally spaced from the first integrated circuit die;
• coupling the first integrated circuit die and the second integrated circuit die to a substrate, the substrate having a substrate top side adjacent the first integrated circuit die and second integrated circuit die, and a substrate bottom side opposite the top side, wherein forming the substrate comprises:
• embedding a bridge in the substrate, the bridge having a bridge top surface, a bridge bottom surface, the bridge top surface being closer to the first integrated circuit die than the bridge bottom surface is, the bridge having a bridge height measured between the bridge top surface and the bridge bottom surface, and the bridge having a first bridge contact pad at the bridge top surface;
• forming a first bridge via extending from the first bridge contact pad away from the bridge top surface, the first bridge via having a first bridge via height;
• forming a first bridge contact extending from a top of the first bridge via towards the first integrated circuit die, the first bridge contact having a first width, the first bridge contact being electrically coupled to the first die interconnect structure;
• forming a first non-bridge via laterally spaced from the embedded bridge, the first non-bridge via having a first non-bridge via height greater than the first bridge via height, wherein the first non-bridge via has a top surface above a top surface of the first bridge contact pad;
• forming a first conductive portion of a redistribution layer above and electrically coupled to the first non-bridge via;
• and
• forming a first non-bridge contact laterally spaced away from the bridge and above and electrically coupled to the first conductive portion of the redistribution layer, the first non-bridge contact positioned so that a line parallel to the bridge top surface intersects both the first bridge contact and the first non-bridge contact, the first non-bridge contact having a second width greater than the first width of the first bridge contact, the first non-bridge contact being electrically coupled to the second die interconnect structure.