Gate Formation Of Semiconductor Devices

A system, comprising:

• a gate formation tool configured to form a dummy gate stack and a metal gate stack replacing the dummy gate stack;
• a gate length measuring tool configured to measure a gate length of the dummy gate stack at a height of the dummy gat stack that is lower than a top surface of a fin engaged by the dummy gate stack;
• and
• a determination unit configured to pick an etching recipe from a series of etching recipes based on the measured gate length of the dummy gate stack, wherein the gate formation tool is also configured to etch the dummy gate stack with the picked etching recipe to form a gate trench for filling the metal gate stack therein.

A semiconductor device, comprising:

• an active region above a substrate, wherein the active region extends lengthwise along a first direction;
• a metal gate disposed on sidewalls and a top surface of the active region, wherein the metal gate extends lengthwise along a second direction generally perpendicular to the first direction, wherein the metal gate includes a gate dielectric layer in direct contact with the active region and a gate electrode layer over the gate dielectric layer;
• a gate spacer disposed on sidewalls of the metal gate, wherein the gate spacer is in direct contact with the sidewalls of the metal gate;
• and
• a dielectric feature disposed on the sidewalls of the active region, wherein the dielectric feature is stacked between a portion of the gate spacer and the metal gate.