Methods of forming microelectronic devices, and related electronic systems

A method of forming a memory device, comprising:

• forming a first microelectronic device construction comprising control logic devices;
• forming a second microelectronic device construction comprising:
• a carrier structure;
• a stack structure overlying the carrier structure and comprising multiple tiers vertically adjacent one another, each tier of the multiple tiers comprising a conductive structure and an insulating structure vertically adjacent the conductive structure;
• strings of memory cells each vertically extending through the multiple tiers of the stack structure;
• conductive digit lines vertically overlying the stack structure and coupled to the strings of memory cells;
• dielectric cap structures directly vertically overlying the conductive digit lines;
• a dielectric material horizontally intervening between the conductive digit lines and horizontally intervening between the dielectric cap structures;
• air gaps surrounded by the dielectric material, the air gaps horizontally intervening between and vertically overlapping the conductive digit lines;
• and
• conductive contact structures vertically extending through the dielectric cap structures and directly physically contacting the conductive digit lines, the conductive contact structures partially vertically overlapping the air gaps;
• attaching the second microelectronic device construction to the first microelectronic device construction to form a microelectronic device structure assembly, the conductive digit lines vertically interposed between the stack structure and the control logic devices within the microelectronic device structure assembly;
• removing the carrier structure from the microelectronic device structure assembly;
• and
• forming at least one source structure over the stack structure of the microelectronic device structure assembly.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a memory device operably coupled to the processor device and comprising:
• a stack structure comprising multiple tiers vertically adjacent one another, each tier of the multiple tiers comprising a conductive structure and an insulative structure vertically adjacent the conductive structure;
• a source structure vertically overlying the stack structure;
• conductive digit lines vertically underlying the stack structure;
• strings of memory cells each vertically extending through the multiple tiers of the stack structure and coupled to the source structure and the conductive digit lines;
• dielectric nitride structures directly vertically underlying the conductive digit lines;
• insulative material horizontally interposed between the conductive digit lines and horizontally interposed between the dielectric nitride structures;
• air gaps within the insulative material, the air gaps vertically overlapping and horizontally interposed between the conductive digit lines;
• conductive contacts vertically extending through the dielectric nitride structures and directly physically contacting the conductive digit lines, the conductive contacts partially vertically overlapping the air gaps;
• conductive pads vertically underlying and coupled to the conductive contacts;
• and
• control logic circuitry vertically underlying and coupled to the conductive pads.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a memory device operably coupled to the processor device and comprising:
• a stack structure comprising multiple tiers vertically adjacent one another, each tier of the multiple tiers comprising a conductive structure and an insulative structure vertically adjacent the conductive structure;
• a source structure vertically overlying the stack structure;
• conductive digit lines vertically underlying the stack structure;
• strings of memory cells each vertically extending through the multiple tiers of the stack structure and coupled to the source structure and the conductive digit lines;
• dielectric nitride structures directly vertically underlying the conductive digit lines;
• insulative material horizontally interposed between the conductive digit lines and horizontally interposed between the dielectric nitride structures;
• air gaps within the insulative material, the air gaps vertically overlapping and horizontally interposed between the conductive digit lines;
• conductive contacts vertically extending through the dielectric nitride structures and directly physically contacting the conductive digit lines, the conductive contacts partially vertically overlapping the air gaps;
• conductive pads vertically underlying and coupled to the conductive contacts;
• and
• control logic circuitry vertically underlying and coupled to the conductive pads.

An electronic system, comprising:

• a processor device operably coupled to an input device and an output device;
• and
• a memory device operably coupled to the processor device and comprising:
• a control circuitry structure including control logic circuitry;
• a memory array structure vertically above and bonded to the control circuitry structure, the memory array structure comprising:
• conductive digit line structures;
• air gaps vertically overlapping and horizontally interposed between the conductive digit line structures;
• a stack structure vertically above the conductive digit line structures and the air gaps, the stack structure comprising tiers vertically stacked relative to one another and respectively comprising conductive material and insulative material vertically neighboring the conductive material;
• and
• pillar structures respectively comprising semiconductor material vertically extending through the tiers of the stack structure;
• and
• a source structure comprising doped semiconductor material vertically above the stack structure and in physical contact with the semiconductor material of the pillar structures.