Semiconductor device structure with vertical transistor over underground bit line

A semiconductor device structure comprising:

• a semiconductor substrate with a semiconductor surface;
• an active region, and a STI region surrounding the active region;
• and
• a transistor within the active region, and the transistor comprising a gate structure, a first conductive region, and a second conductive region;
• wherein the second conductive region is above the first conductive region and comprises two sub-regions located on two sides of the gate structure respectively;
• wherein the first conductive region comprises a lighted doped region, and a top surface of the lighted doped region is aligned or substantially aligned with an edge of the gate structure.

A semiconductor device structure comprising:

• a semiconductor bulk substrate with an original surface;
• an active region within the bulk semiconductor substrate, wherein the active region comprises a plurality of transistors, each transistor comprises a gate structure with a bottom surface under the original surface, a first conductive region coupled to the bulk substrate, and a second conductive region;
• a STI region surrounding the active region;
• and
• an interconnection layer extended beyond at least one transistor of the plurality of transistors and electrically coupled to the at least one transistor at a connection position under the gate structure of the at least one transistor;
• wherein the first conductive region of the at least one transistor comprises a lighted doped region and a highly doped region surrounded by the lighted doped region, and a top surface of the lighted doped region is aligned or substantially aligned with an edge of the gate structure of the at least one transistor.