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US 2025/0149098 A1Published application
Memory device
AssigneeKioxia Corporation
InventorHiroshi MAEJIMA
Life of this patent
Estimating the term…
Abstract
A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.
Claims8
1-19. (canceled)
A memory device, comprising:
- a first chip including:
- a first memory cell and a second memory cell, each of the first memory cell and the second memory corresponding to a column address;
- a first bit line connected to the first memory cell;
- a first bonding pad connected to the first bit line;
- a second bit line connected to the second memory cell;
- and
- a second bonding pad connected to the second bit line;
- and
- a second chip including:
- a third bonding pad connected to the first bonding pad;
- a fourth bonding pad connected to the fourth bonding pad;
- and
- a sense amplifier unit including a first transistor connected to the first bit line through the first bonding pad and the third bonding pad and a second transistor connected to the second bit line through the second bonding pad and the fourth bonding pad.
10 more elements
A memory device, comprising:
- a first chip including:
- a first memory cell and a second memory cell, each of the first memory cell and the second memory corresponding to a column address;
- a first bit line coupled to the first memory cell;
- a first bonding pad coupled to the first bit line;
- a second bit line coupled to the second memory cell;
- and
- a second bonding pad coupled to the second bit line;
- and
- a second chip including:
- a third bonding pad in direct contact with the first bonding pad;
- a fourth bonding pad in direct contact with the fourth bonding pad;
- and
- a sense amplifier unit including a first transistor coupled to the first bit line through at least the first bonding pad and the third bonding pad and a second transistor coupled to the second bit line through at least the second bonding pad and the fourth bonding pad.
10 more elements
Dependencies are inferred from the claim text.