All level coarse/fine programming of memory cells

A system, comprising:

• a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
• and
• a controller coupled to the memory array, the controller to perform operations comprising:
• identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines;
• causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a sequence of time periods;
• causing a second voltage to be applied to a first bitline over the sequence of time periods;
• causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the sequence of time periods, wherein the second time period follows a first time period;
• causing a fourth voltage to be applied to a third bitline over the sequence of time periods.

A system, comprising:

• a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
• and
• a controller coupled to the memory array, the controller to perform operations comprising:
• identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines;
• causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a sequence of time periods;
• causing a second voltage to be applied to a first bitline over the sequence of time periods;
• causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the sequence of time periods, wherein the second time period follows a first time period;
• and
• causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.