Memory device for implementing multi-level memory and method of implementing multi-level memory by using the memory device

A method of implementing a multi-level memory by using a memory device, the memory device comprising:

• first and second electrodes apart from each other;
• a self-selecting memory layer between the first and second electrodes, having an ovonic threshold switching characteristic, comprising a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and a strength of a voltage applied thereto;
• and
• a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto,
• wherein the method comprises:
• implementing multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, a pulse height, and a pulse width of a voltage applied between the first and second electrodes.

A memory device comprising:

• a plurality of bit lines;
• a plurality of word lines intersecting the plurality of bit lines;
• and
• a plurality of memory cells where the plurality of bit lines and the plurality of word lines intersect each other,
• wherein each of the plurality of memory cells comprises:
• first and second electrodes apart from each other;
• a self-selecting memory layer between the first and second electrodes, having an ovonic threshold switching characteristic, comprising a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and a strength of a voltage applied thereto;
• and
• a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto,
• wherein the memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, a pulse height, and a pulse width of a voltage applied between the first and second electrodes.

A multi-level memory device comprising:

• a self-selecting memory device having an ovonic threshold switching characteristic and having a threshold voltage varying depending on a polarity and strength of a voltage applied thereto;
• a resistive memory device connected in series to the self-selecting memory device and having a resistance characteristic varying depending on a voltage applied thereto;
• and
• a memory controller configured to change a height of a pulse voltage of negative (−) polarity applied to the self-selecting memory device.