Input/output interface circuit and memory system including the same

An input/output interface circuit comprising:

• a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal;
• and
• a first sub-channel and a second sub-channel connected to the common receiving driver, wherein:
• the first sub-channel is configured to receive the first clock signal and a first chip select signal, output a 2-1-th clock signal through a first logical AND operation of the first clock signal and the first chip select signal, output a first single clock signal provided from among:
• i) the 2-1-th block signal and ii) one or more first divided clock signals, wherein the one or more first divided clock signals are divided from the 2-1-th clock signal, and sample a first command address signal using the first single clock signal, and
• the second sub-channel is configured to receive the first clock signal and a second chip select signal, output a 2-2-th clock signal through a second logical AND operation of the first clock signal and the second chip select signal, and output a second single clock signal provided from among:
• i) the 2-2-th block signal and ii) one or more second divided clock signals, wherein the one or more first divided clock signals are divided from the 2-2-th block signal, and sample a second command address signal using the second single clock signal.

A memory system comprising:

• a system-on-chip (SoC) comprising a first input/output interface circuit;
• and
• a memory device comprising a second input/output interface circuit communicating with the first input/output interface circuit, wherein the second input/output interface circuit comprises:
• a common receiving driver configured to receive a differential clock signal through the first input/output interface circuit and output a first clock signal corresponding to the differential clock signal;
• and
• a pair of sub-channels connected to the common receiving driver, and
• each sub-channel of the pair of sub-channels is configured to receive the first clock signal through the common receiving driver,
• a chip select signal, a second clock signal, a logical AND operation, a single clock signal, one or more divided clock signals, and a command address signal are separately defined for each sub-channel,
• each sub-channel is configured to receive the chip select signal,
• each sub-channel is configured to output the second clock signal through the logical AND operation of the first clock signal and the chip select signal to provide the single clock signal, wherein the single clock signal is provided from among:
• i) the second clock signal and ii) the one or more divided clock signals, wherein the one or more divided clock signals are divided from the second clock signal, and
• the single clock signal is configured to sample the command address signal.