Semiconductor device and memory module
AssigneeRenesas Electronics Corporation
InventorsKazunori YAMANE, Takanori AKASHIGE
Life of this patent
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Abstract
To provide a semiconductor device and a memory module capable of correctly maintaining the phase relationship between a data signal and a data strobe signal that determines the latch timing of the data signal. A variable delay circuit VDLYs_A generates respective data strobe signals DQSin, DQSin_M by delaying an input data strobe signal MDQS by delay amounts ST1, ST2. A timing adjustment circuit TMCT adjusts the delay amount ST1 based on the determination of matching/mismatching between a data signal DQo from a main slicer SLr and a data signal DQo_M from a monitor slicer SLr_M, while changing the delay amount ST2,
Claims15
A semiconductor device comprising:
- a first data holding circuit for latching an input data signal in synchronization with a first data strobe signal;
- a second data holding circuit for latching the input data signal in synchronization with a second data strobe signal;
- a variable delay circuit for generating the first and second data strobe signals by delaying an input data strobe signal by a first delay amount and a second delay amount, respectively;
- and
- a timing adjustment circuit for setting the first and second delay amounts in the variable delay circuit,
- wherein the timing adjustment circuit adjusts the first delay amount based on a determination of a match/mismatch between a first data signal from the first data holding circuit and a second data signal from the second data holding circuit while changing the second delay amount.
A memory module comprising:
- a module wiring board having control external terminals and data external terminals;
- multiple DDR-SDRAM chips mounted on the module wiring board;
- a registered clock driver mounted on the module wiring board for re-driving a memory control signal input through the control external terminals and outputting to the multiple DDR-SDRAM chips;
- and
- a data buffer mounted on the module wiring board for re-driving data signals and data strobe signals input through the data external terminals and outputting to the multiple DDR-SDRAM chips, and for re-driving input data signals and input data strobe signals from the multiple DDR-SDRAM chips and outputting to the data external terminals,
- wherein the data buffer has a first data holding circuit for latching the input data signal in synchronization with a first data strobe signal, a second data holding circuit for latching the input data signal in synchronization with a second data strobe signal, a variable delay circuit for generating the first and second data strobe signals by delaying the input data strobe signal by the first and second delay amounts, respectively, and a timing adjustment circuit for setting the first and second delay amounts in the variable delay circuit, and
- wherein the timing adjustment circuit adjusts the first delay amount based on the determination of whether the first data signal from the first data holding circuit matches or does not match the second data signal from the second data holding circuit, while varying the second delay amount.
Dependencies are inferred from the claim text.