Circuit and method of operating the same

A circuit comprising:

• a power control circuit coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage, the power control circuit configured to generate a first output control signal, a second output control signal and a third output control signal in response to a first control signal, a second control signal or a third control signal, at least the first voltage or the first control signal having a first voltage swing, and at least the second voltage or the second control signal having a second voltage swing different from the first voltage swing, the first control signal causing the power control circuit to enter a power management mode having a first reduced power state and a second reduced power state;
• a first header circuit coupled to the power control circuit, and configured to supply at least a first supply voltage, a second supply voltage or a third supply voltage in response to at least the first output control signal, the second output control signal or the third output control signal;
• and
• a first peripheral circuit coupled to the first header circuit, and being configured to receive the second supply voltage;
• wherein the power management mode includes the second voltage supply being turned off;
• and
• wherein the power control circuit comprises:
• a second header circuit coupled to the first voltage supply and the second voltage supply, and configured to supply at least the first voltage of the first voltage supply to a first voltage supply node in response to the first control signal, or the second voltage of the second voltage supply to a second voltage supply node in response to a first level shifted signal, the first level shifted signal is a level shifted version of the first control signal.

A method of operating a circuit, the method comprising:

• generating, by a power control circuit, a first output control signal, a second output control signal and a third output control signal in response to at least a first control signal or a second control signal, the power control circuit being coupled to a first voltage supply having a first voltage and a second voltage supply having a second voltage, at least the first voltage or the first control signal having a first voltage swing, and at least the second voltage or the second control signal having a second voltage swing different from the first voltage swing;
• supplying, by a first header circuit, at least a first supply voltage to a memory cell array, a second supply voltage to a first peripheral circuit or a third supply voltage to a second peripheral circuit in response to at least the first output control signal, the second output control signal or the third output control signal;
• supplying, by a second header circuit, at least the first voltage of the first voltage supply to a first voltage supply node in response to the first control signal, or supplying the second voltage of the second voltage supply to a second voltage supply node in response to a first level shifted signal, the first voltage supply node being different than the second voltage supply node, the first level shifted signal is a level shifted version of the first control signal, wherein the second header circuit is coupled to at least a first level shifter circuit;
• and
• causing the memory cell array to enter a first reduced power state or a second reduced power state in response to a first value of the first control signal, wherein causing the memory cell array to enter the first reduced power state or the second reduced power state comprises:
• turning off the second voltage supply.