Logic cell structures and related methods

An integrated circuit logic cell structure, comprising:

• a first input node;
• a second input node;
• and
• a pulling network comprising a plurality of transistor segments, each of the plurality of transistor segments comprising a gate region, a first source/drain region and a second source/drain region, wherein each of the plurality of transistor segments comprises a substantially identical width;
• wherein the first input node is electrically connected to the gate region of a first number of the transistor segments and the second input node is electrically connected to the gate region of a second number of the transistor segments;
• wherein the first number is associated with a first current-driving capability and the second number is associate with a second current-driving capability different from the first current-driving capability.

An integrated circuit logic cell structure, comprising:

• a first input node;
• a second input node;
• and
• a pulling network comprising a plurality of transistor segments, each of the plurality of transistor segments comprising a gate region, a first source/drain region and a second source/drain region, wherein each of the plurality of transistor segments comprises a substantially identical width;
• wherein the first input node is electrically connected to the gate region of a first number of the transistor segments and the second input node is electrically connected to the gate region of a second number of the transistor segments;
• wherein the first input node and the second input node have different current-driving capabilities provided by the plurality of transistor segments.