Full-analog vector matrix multiplication processing-in-memory circuit and operation method thereof, computer device, and computer-readable storage medium

Abstract

A full-analog vector matrix multiplication process-in-memory circuit comprises: an input circuit, a device array, an output clamping circuit, and an analog shift-and-add unit. The input circuit is used for sampling and holding analog input data and inputting the sampled analog input data into an array. The device array consists of resistive devices and is used for storing a weight value in the form of conductance and performing vector matrix multiplication calculation on the analog input data and the weight value. The output clamping circuit is used for clamping an output point of the device array to a zero level and converting a calculation result in the form of current into a result in the form of voltage for output. The analog shift-and-add unit is used for shifting and adding calculation results of devices in columns of the device array to complete carry calculation.

Dependencies are inferred from the claim text.