Interface and microcontroller

An I/O circuit block according to any one of the preceding claims wherein instructions executed by the state machine include an operation to set a value to at least one of the plurality of terminals concurrently with execution of another operation defined by the instruction.

An I/O circuit block according to any one of the preceding claims wherein the register unit comprises an input FIFO register and an output FIFO register, the input FIFO register and the output FIFO register being configurable as a single, double length FIFO register for input or output.

An I/O circuit block according to any one of the preceding claims wherein the state machine comprises an input shift register and an output shift register and is operable in an auto pull mode wherein a first predetermined number of bits are transferred from the register unit to the output shift register when the content of the output shift register is less than a first threshold and/or in an auto push mode wherein a second predetermined number of bits are transferred to the register unit from the input shift register when the content of the input shift register is greater than a second threshold.

An I/O circuit block according to any one of the preceding claims wherein the state machine is configured to also execute instructions from one or more of:

• the register unit, a shift register within the state machine and a configuration register within the state machine.

An I/O circuit block according to any one of the preceding claims wherein the state machine comprises a wrap control field specifying a sequence of instructions which are executed repeatedly.

An I/O circuit block according to any one of the preceding claims wherein the state machine comprises a configurable clock divider to enable the state machine to operate at a lower clock rate than an external clock.

An I/O circuit block according to any one of the preceding claims having a plurality of state machines and a corresponding plurality of register units.

An integrated circuit comprising at least one I/O circuit block according to any one of the preceding claims.