Read Arbiter Circuit with Dual Memory Rank Support

A method, comprising:

• receiving, by a memory control circuit, a first set of read requests to a first memory rank of a plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks, wherein a given memory rank includes a plurality of memory circuits coupled to a common communication bus;
• determining, by the memory control circuit and based on a determination that at least one quality-of service requirement is not satisfied, to perform only one rank switch for a first read turn in which read requests are processed against the plurality of memory ranks;
• processing, by the memory control circuit, first ones of the first set of read requests against the first memory rank during the first read turn;
• in response to completing the processing, the memory control circuit performing the one rank switch from the first memory rank to the second memory rank;
• and
• in response to completing the rank switch, the memory control circuit processing second ones of the second set of read requests against the second memory rank during the first read turn.

A system, comprising:

• a plurality of memory ranks, a given one of which includes a plurality of memory circuits coupled to a common communication bus;
• at least one processor circuit configured to issue memory requests, including read and write requests, directed to ones of the plurality of memory ranks;
• and
• a memory control circuit configured to:
• receive, from the at least one processor circuit, a first set of read requests to a first memory rank of the plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks;
• process particular read requests of the first and second sets of read requests during a read turn using only one rank switch between the first and second memory ranks in response to a determination that at least one quality-of-service requirement associated with the first and second sets of read requests is not satisfied;
• and
• process the particular read requests of the first and second sets during the read turn using a plurality of rank switches between the first and second memory ranks in response to a determination that the at least one quality-of-service requirement is satisfied.