Cache evict duplication management

A computer program product embodied in a non-transitory computer readable medium for cache management, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache, and wherein the plurality of processor cores implements special cache coherency operations;
• coupling an evict buffer to the plurality of processor cores, wherein the evict buffer is shared among the plurality of processor cores, and wherein the evict buffer enables delayed writes;
• monitoring evict buffer writes, wherein the monitoring evict buffer writes identifies a special cache coherency operation;
• and
• marking an evict buffer entry, wherein the marking corresponds to the special cache coherency operation that was identified, and wherein the marking enables management of cache evict duplication.

A computer system for cache management comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache, and wherein the plurality of processor cores implements special cache coherency operations;
• couple an evict buffer to the plurality of processor cores, wherein the evict buffer is shared among the plurality of processor cores, and wherein the evict buffer enables delayed writes;
• monitor evict buffer writes, wherein the monitoring evict buffer writes identifies a special cache coherency operation;
• and
• mark an evict buffer entry, wherein the marking corresponds to the special cache coherency operation that was identified, and wherein the marking enables management of cache evict duplication.