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US 2025/0147891 A1Published application
Cache layout optimization
AssigneeDell Products L.P.
InventorsMalak Alshawabkeh, Kaustubh Sahasrabudhe, Ramesh Doddaiah
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Abstract
One or more aspects of the present disclosure relate to cache layout optimization. In embodiments, an input/output (IO) workload is received by a storage array. Further, cache slot allocations are dynamically adjusted for each cache segment of global memory based on one or more characteristics of the IO workload.
Claims20
A method comprising:
- receiving an input/output (IO) workload by a storage array;
- and
- dynamically adjusting cache slot allocations for each cache segment of global memory based on one or more characteristics of the IO workload, wherein dynamically adjusting cache slot allocations comprises:
- analyzing the IO workload using a neural self-learning architecture to process current and historical IO metadata,
- generating cache layout models using a holt-winters forecasting technique,
- establishing distinct cache slot sizes for different cache segments, and
- determining IO characteristics, including IO type, size, pattern, and sequence.
4 more elements
An apparatus with a memory and processor, the apparatus configured to:
- receive an input/output (IO) workload by a storage array;
- and
- dynamically adjusting cache slot allocations for each cache segment of global memory based on one or more characteristics of the IO workload, wherein dynamically adjusting cache slot allocations comprises:
- analyzing the IO workload using a neural self-learning architecture to process current and historical IO metadata,
- generating cache layout models using a holt-winters forecasting technique,
- establishing distinct cache slot sizes for different cache segments, and determining IO characteristics, including IO type, size, pattern, and sequence.
3 more elements
Dependencies are inferred from the claim text.