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US 2025/0147882 A1Published application
Board level dynamic cache layout distribution
AssigneeDell Products L.P.
InventorJohn Creed
Life of this patent
Estimating the term…
Abstract
One or more aspects of the present disclosure relate to cache layout optimization. In embodiments, an input/output (IO) workload is received by a storage array. Additionally, a system-level cache layout distribution model is established based on one or more characteristics of the IO workload. Further, cache slot allocations are dynamically adjusted for each cache segment of global memory for each board based on the system-level cache layout distribution model and the one or more characteristics of the IO workload.
Claims20
A method comprising:
- receiving an input/output (IO) workload by a storage array;
- dynamically establishing a system-level cache layout distribution model based on one or more characteristics of the IO workload;
- and
- dynamically adjusting cache slot allocations for each cache segment of global memory for each board based on the system-level cache layout distribution model and the one or more characteristics of the IO workload.
1 more element
An apparatus with a memory and processor, the apparatus configured to:
- receive an input/output (IO) workload by a storage array;
- dynamically establish a system-level cache layout distribution model based on one or more characteristics of the IO workload;
- and
- dynamically adjust cache slot allocations for each cache segment of global memory based for each board based on the system-level cache layout distribution model and the one or more characteristics of the IO workload.
1 more element
Dependencies are inferred from the claim text.