US 2025/0147764 A1 · PROCESSOR IDENTIFICATION

Abstract

The present description concerns a device comprising a bus, peripherals coupled to the bus, the peripherals comprising a first circuit, processors coupled to the bus and initiating accesses to the peripherals, each comprising an address phase followed by a data phase, and for each processor, a second circuit delivering an identifier of the processor over the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores the identifier present over the bus during the address phase of the access, and then delivers the identifier stored over the bus during the data phase of the access.

Claims20

Dependent claims

A device comprising:

a bus;
processors coupled to the bus, and configured to execute a same instruction set and initiate accesses to peripherals via the bus, each access comprising an address phase followed by a data phase;
for each processor, a second circuit associated with the processor and configured to provide an identifier of the processor on the bus during the address phase of each access initiated by the processor;
and
the peripherals, coupled to the bus, the peripherals comprising a first circuit configured to, at each read access to the first circuit initiated by one of the processors:
store the identifier present on the bus during the address phase of the access;
and
provide the bus with the stored identifier during the data phase of the access.

5 more elements

Dependencies are inferred from the claim text.

Processor identification

Life of this patent

Processor identification

Life of this patent

Abstract

Claims20