Multiple register allocation sizes for gpu hardware threads

A method for comprising:

• receiving a request to dispatch program code for execution to a processing resource within a graphics core of a graphics processor;
• determining whether variable registers per thread (VRT) is enabled for the program code;
• statically configuring the processing resource within the graphics core that was selected to execute the program code with a default number of registers per thread in response to a determination that VRT is not enabled for the program code;
• dynamically allocating registers to a hardware thread of the processing resource according to a register configuration associated with the program code in response to a determination that VRT is enabled for the program code;
• and
• executing an instruction of the program code via the hardware thread.

A graphics processing system comprising:

• a memory interface;
• a processing cluster coupled with the memory interface, the processing cluster including a plurality of graphics cores coupled via a data interconnect;
• and
• circuitry to dispatch workloads for execution by processing resources within a graphics core of the plurality of graphics cores, the circuitry configured to:
• receive a request to dispatch program code for execution, the program code associated with a register configuration selected from a plurality of register configurations;
• select a processing resource of a plurality of processing resources within the graphics core, the processing resource determined to have sufficient available resources to satisfy the register configuration for the program code;
• assign a number of registers to a hardware thread of the processing resource based on the register configuration selected for the program code;
• and
• execute an instruction of the program code via the hardware thread.