Parallel polynomial modular multiplication using ntt and inverse ntt
OwnerKeshab K. Parhi, Weihang Tan +3inventors
InventorsKeshab K. Parhi, Weihang Tan, Sin-Wei Chiu, Antian Wang, Yingjie Lao
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OwnerKeshab K. Parhi, Weihang Tan +3inventors
InventorsKeshab K. Parhi, Weihang Tan, Sin-Wei Chiu, Antian Wang, Yingjie Lao
Estimating the term…
A method comprises receiving a modulus for a number-theoretic transform of a polynomial and selecting a plurality of prime moduli whose product forms the modulus for the number-theoretic transform, wherein the plurality of prime moduli are selected by giving preference to prime moduli having fewer ones in a binary representation of the prime moduli. For each prime modulus in the plurality of prime moduli: dividing a coefficient of the polynomial into segments and performing modular reduction of the segments relative to the prime modulus. Performing the modular reduction of at least one segment comprises implementing a multiplication of a value by a modular reduction of a base value relative to the prime modulus using a shift-add-unit having a smaller area requirement than a modular multiplier. A modular reduction of the coefficient relative to the prime modulus is determined based on the modular reductions of the segments.
A method of reducing chip area required to perform a number-theoretic transform of a polynomial using parallel processing, the method comprising:
A specialized circuit for performing a number-theoretic transform, the specialized circuit comprising:
A circuit comprising:
Dependencies are inferred from the claim text.