Binary floating-point in-memory multiplication device

An operating method of a floating-point in-memory multiplication device that performs multiplication on a multiplicand and a multiplier to generate a first product, the floating-point in-memory multiplication device comprising a binary in-memory multiplier circuit and an encoder circuit, wherein each of the multiplicand, the multiplier and the first product is a binary floating-point number in IEEE 754 format and consists of a sign bit, a q-bit exponent and a (p−1)-bit significand, the method comprising the steps of:

• performing a XOR operation over sign bits of the multiplicand and the multiplier to obtain a sign bit of the first product;
• respectively obtaining a first prefix bit and a second prefix bit according to the q-bit exponent of the multiplicand and the q-bit exponent of the multiplier such that the first prefix bit and the (p−1)-bit significand of the multiplicand form a first p-bit significand, and the second prefix bit and the (p−1)-bit significand of the multiplier form a second p-bit significand;
• adding up the q-bit exponent of the multiplicand and the q-bit exponent of the multiplier to obtain a (q+1)-bit temporary exponent;
• performing multiplication on the first and the second p-bit significands by the binary in-memory multiplier circuit to obtain a 2p-bit second product;
• identifying and transforming a target bit position among the most significant p bits of the 2p-bit second product into a shift distance x by the encoder circuit, wherein the target bit position contains a nonzero value and is closest to a most significant bit position of the 2p-bit second product;
• calculating a q-bit exponent of the first product by the encoder circuit according to the (q+1)-bit temporary exponent and a value of (2−2q-1−z);
• and
• shifting the 2p-bit second product to the left by z bit positions by the encoder circuit to obtain a (p−1)-bit significand of the first product;
• wherein 0<=z<=(p−1) and (p+q)>=8.