Dram and control method for the same
AssigneeResearch & Business Foundation Sungkyunkwan University
InventorsJUNGRAE KIM, Jae Yoon LEE
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Abstract
There is provided a DRAM including a plurality of mats composed of cell arrays, comprising: a first mat including a first cell array that is aligned by first bitlines and first wordlines; a second mat including a second cell array that is adjacent to the first mat and aligned by second bitlines and second wordlines; and a bitline sense amplifier shared by the first bitlines of the first mat and the second bitlines of the second mat, wherein the bitline sense amplifier connected to the first mat is shared only with the second mat.
Claims20
A DRAM (Dynamic Random Access Memory) including a plurality of mats composed of cell arrays, comprising:
- a first mat including a first cell array that is aligned by first bitlines and first wordlines;
- a second mat including a second cell array that is adjacent to the first mat and aligned by second bitlines and second wordlines;
- and
- a bitline sense amplifier shared by the first bitlines of the first mat and the second bitlines of the second mat,
- wherein the bitline sense amplifier connected to the first mat is shared only with the second mat.
A method for controlling a DRAM including a bitline sense amplifier shared by first bitlines of a first mat and second bitlines of a second mat adjacent to the first mat, the method comprising:
- identifying memory usage and an application operation method of a server to which the DRAM belongs;
- selecting one of a basic mode, a low-latency mode, or a low-power mode based on the memory usage and the application operating method;
- and
- controlling the first mat and the second mat according to the selected mode,
- wherein the bitline sense amplifier connected to the first mat is shared only with the second mat.
A method for controlling a DRAM including a bitline sense amplifier shared by first bitlines of a first mat and second bitlines of a second mat adjacent to the first mat, the method comprising:
- identifying memory usage and an application operation method of a server to which the DRAM belongs;
- selecting one of a basic mode, a low-latency mode, or a low-power mode based on the memory usage and the application operating method;
- and
- controlling the first mat and the second mat according to the selected mode,
- wherein the low-power mode has a second update cycle longer than a first update cycle of the basic mode and the low-latency mode, and
- the bitline sense amplifier connected to the first mat is shared only with the second mat.
Dependencies are inferred from the claim text.