Self-Learning Data Linearizer

A circuit, comprising:

• a first intermediate memory communicatively coupled to a vector processor, a scalar processor, and a RAM, the RAM to store a vector program for performing calculations;
• an address sequence memory to store non-linear RAM addresses corresponding to linear locations in the first intermediate memory;
• an address learning agent to, while the scalar processor performs the calculations of the program:
• capture a first set of memory access addresses issued by the scalar processor to the RAM during processing of a first frame of data;
• map the set of memory access addresses to linear locations in the first intermediate memory;
• and
• store in the address sequence memory the mapping of the set of memory access addresses to the linear locations in the first intermediate memory;
• and
• a data sequencer to read a first frame of data from the RAM and store the first frame of data to the first intermediate memory based on addresses stored in the prefetch address lookup table,
• the first intermediate memory to thereby provide linearized data to the vector processor to execute a vector instruction.

A method comprising:

• reading a sequence of non-contiguous addresses from an address sequence memory;
• prefetching a first frame of data from a RAM using the sequence of non-contiguous addresses;
• storing that first frame of data in a first intermediate memory as a first linearized frame of data;
• receiving a vector load instruction to load a portion of the first frame of data;
• loading the portion of the first frame of data into the vector processor from the first intermediate memory;
• and
• executing the vector instruction with the received portion of the first frame of data as an operand.