System for mutual inductance cancellation for x-type multilevel converters

An X-type multilevel power converter for a multi-phase electric power inverter, the X-type multilevel power converter comprising:

• a solid-state integrated circuit (IC) having:
• a positive direct current (DC) power bus;
• a negative DC power bus;
• a first neutral bus;
• a second neutral bus;
• a first alternating current (AC) bus;
• a second AC bus;
• a plurality of semiconductor switches interconnected via the positive DC power bus, the negative DC power bus, the first neutral bus, and the second neutral bus, the plurality of semiconductor switches including:
• a first semiconductor switch connected at a first node;
• a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch arranged in series with the second semiconductor switch between the first AC bus and the positive DC power bus, wherein the first AC bus is connected at a second node;
• a third semiconductor switch connected at a third node, wherein the second semiconductor switch is connected to the third semiconductor switch at the second node, the second semiconductor switch arranged in series with the third semiconductor switch between the positive DC power bus and the negative DC power bus;
• a fourth semiconductor switch connected to the third semiconductor switch at the third node, wherein the third semiconductor switch is arranged in series with the fourth semiconductor switch between the first AC bus and the negative DC power bus;
• a fifth semiconductor switch connected at a fourth node;
• a sixth semiconductor switch connected to the fifth semiconductor switch at the fourth node, wherein the fifth semiconductor switch is arranged in series with the sixth semiconductor switch between the second AC bus and the positive DC power bus, wherein the second AC bus is connected to a fifth node;
• a seventh semiconductor switch connected to a sixth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at the fifth node, the sixth semiconductor switch arranged in series with the seventh semiconductor switch between the positive DC bus and the negative DC power bus;
• an eighth semiconductor switch connected to the seventh semiconductor switch at the sixth node, wherein the seventh semiconductor switch is arranged in series with the eighth semiconductor switch between the second AC bus and the negative DC power bus;
• a first power diode having a first end connected at the first node and the first power diode having a second end connected at the sixth node via the first neutral bus;
• a second power diode having a first end connected at the third node and the second power diode having a second end connected at the fourth node via the second neutral bus;
• a first heat sink adjoined to the positive DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate;
• and
• a second heat sink adjoined to the negative DC power bus of the solid-state IC via a second DBC substrate.

An electrified vehicle, comprising:

• an electric propulsion system including:
• an electric motor configured to provide power to the electric propulsion system;
• a multi-phase inverter including a plurality of X-type multilevel power converters arranged between a high-voltage direct current (DC) power supply and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC) including:
• a positive DC power bus;
• a negative DC power bus;
• a first neutral bus;
• a second neutral bus;
• a first alternating (AC) bus;
• a second AC bus;
• a plurality of semiconductor switches interconnected via the positive DC power bus, the negative DC power bus, the first neutral bus, and the second neutral bus, the plurality of semiconductor switches including:
• a first semiconductor switch connected at a first node;
• a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch arranged in series with the second semiconductor switch between the first AC bus and the positive DC power bus, wherein the first AC bus is connected at a second node;
• a third semiconductor switch connected at a third node, wherein the second semiconductor switch is connected to the third semiconductor switch at the second node, the second semiconductor switch arranged in series with the third semiconductor switch between the positive DC power bus and the negative DC power bus;
• a fourth semiconductor switch connected to the third semiconductor switch at the third node, wherein the third semiconductor switch is arranged in series with the fourth semiconductor switch between the first AC bus and the negative DC power bus;
• a fifth semiconductor switch connected at a fourth node;
• a sixth semiconductor switch connected to the fifth semiconductor switch at the fourth node, wherein the fifth semiconductor switch is arranged in series with the sixth semiconductor switch between the second AC bus and the positive DC power bus, wherein the second AC bus is connected to a fifth node;
• a seventh semiconductor switch connected to a sixth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at the fifth node, the sixth semiconductor switch arranged in series with the seventh semiconductor switch between the positive DC bus and the negative DC power bus;
• an eighth semiconductor switch connected to the seventh semiconductor switch at the sixth node, wherein the seventh semiconductor switch is arranged in series with the eighth semiconductor switch between the second AC bus and the negative DC power bus;
• a first power diode having a first end connected at the first node and the first power diode having a second end connected at the sixth node via the first neutral bus;
• a second power diode having a first end connected at the third node and the second power diode having a second end connected at the fourth node via the second neutral bus;
• a first heat sink adjoined to the positive DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate;
• and
• a second heat sink adjoined to the negative DC power bus of the solid-state IC via a second DBC substrate.