Np5 fractional clock divider

A method, comprising:

• generating first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
• and
• performing a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction.

An apparatus, comprising:

• means for generating first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
• and
• means for performing a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction.

An apparatus, comprising:

• a clock source including an input configured to generate first and second clock signals based on an input clock signal;
• and
• a logic circuit including first and second inputs coupled to first and second outputs of the clock source, respectively, and an output configured to generate an output clock signal with a frequency being substantially a frequency of the input clock signal divided by NP5, where N is an integer and P5 is a half fraction.