Heterogeneous chip stacking structure

A heterogeneous chip stacking structure, comprising:

• a first chip having a plurality of first convex pillar structures gradually formed outward from the first chip within a first predetermined time, wherein each of the first convex pillar structures has a first bonding pad portion;
• and
• a second chip having a plurality of second convex pillar structures gradually formed outward from the second chip within a second predetermined time, wherein each of the second convex pillar structures has a second bonding pad portion;
• wherein the first chip is configured to be disposed on the second chip, and the first bonding pad portions of the first convex pillar structures of the first chip and the second bonding pad portions of the second convex pillar structures of the second chip are in direct contact with each other and tightly coupled with each other, respectively;
• wherein the first convex pillar structure is not formed by directly placing a pre-prepared solder ball on the first chip;
• wherein the second convex pillar structure is not formed by directly placing another pre-prepared solder ball on the second chip.