Image sensor scheme for optical and electrical improvement

An integrated chip, comprising:

• a semiconductor substrate comprising an image sensor region arranged between sidewalls of the semiconductor substrate;
• a plurality of interconnects within a dielectric structure along a first side of the semiconductor substrate;
• one or more dielectric materials arranged along the sidewalls of the semiconductor substrate;
• a conductive core arranged between the sidewalls of the semiconductor substrate and being laterally surrounded by the one or more dielectric materials, wherein the conductive core has a first width, a second width below the first width, and a third width below the second width, the second width being smaller than both the first width and the third width or larger than both the first width and the third width;
• wherein the one or more dielectric materials have a sidewall comprising a curved segment disposed along a side of the conductive core;
• and
• wherein the conductive core is vertically separated from a surface of the dielectric structure facing the semiconductor substrate by a non-zero distance.

A method, comprising:

• forming a gate structure along a first side of a substrate;
• performing a first patterning process on a second side of the substrate to form one or more sidewalls of the substrate, the one or more sidewalls of the substrate forming one or more trenches extending from the second side of the substrate to within the substrate;
• forming one or more dielectric materials within the one or more trenches;
• forming a conductive material onto the one or more dielectric materials and within the one or more trenches;
• and
• forming a conductive interconnect over the second side of the substrate and onto the conductive material.