Compact logic cells using full backside connectivity

A method for fabricating a semiconductor device, the method comprising:

• providing a plurality of integrated circuit cells, comprising, for each of the plurality of integrated circuit cells:
• providing a plurality of gate structures spaced apart from each other by one of a first plurality of source/drain (S/D) structures, each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure and connecting adjacent S/D structures in the first plurality of S/D structures to each other, wherein at least one of the plurality of gate structures forms a gate-all-around (GAA) field effect transistor (FET);
• providing a frontside source/drain contact (FSDC) structure electrically connecting to a top surface of at least one of the first plurality of S/D structures;
• providing a frontside contact over active gate (FSCOAG) structure electrically connecting to a top surface of at least one of the plurality of gate structures;
• providing a frontside inter-layer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures;
• providing a frontside metal zero (FM0) interconnect layer, disposed on the FS-ILD layer, comprising a plurality of parallel FM0 interconnects, at least one of which is electrically connected to the FSDC structure or the FSCOAG structure;
• providing a backside source/drain contact (BSDC) structure electrically connecting to a bottom surface of at least one of the first plurality of S/D structures;
• providing a backside contact over active gate (BSCOAG) structure electrically connecting to a bottom surface of at least one of the plurality of gate structures,
• providing a backside inter-layer dielectric (BS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures;
• and
• providing a backside metal zero (BM0) interconnect layer, disposed on the BS-ILD layer, comprising a plurality of parallel BM0 interconnects, at least one of which is electrically connected to the BSDC structure or the BSCOAG structure.