Integration of silicon channel nanostructures and silicon-germanium channel nanostructures

A method of forming a semiconductor structure, comprising:

• forming a first semiconductor portion stack and a second semiconductor portion stack over a substrate, wherein the first semiconductor portion stack comprises first silicon portions vertically interlaced with first silicon-germanium portions, and the second semiconductor portion stack comprises second silicon portions vertically interlaced with second silicon-germanium portions;
• removing the first silicon-germanium portions;
• removing the second silicon portions;
• and
• forming a first gate structure around middle portions of the first silicon portions and a second gate structure around middle portions of the second silicon-germanium portions by depositing and patterning a gate dielectric material layer and a gate electrode material layer.

A semiconductor structure comprising:

• a first gate-all-around field effect transistor located over a substrate and comprising:
• at least one silicon portion, and
• a first gate structure including a first gate dielectric layer and a first gate electrode and surrounding each middle portion of the at least one silicon portion;
• a second gate-all-around field effect transistor located over the substrate, laterally spaced from the first gate-all-around field effect transistor, and comprising:
• at least one silicon-germanium portion, and
• a second gate structure including a second gate dielectric layer and a second gate electrode and surrounding each middle portion of the at least one silicon-germanium portion, wherein the first gate electrode and the second gate electrode comprise a same conductive material.