Semiconductor structure

A semiconductor structure, comprising:

• a first well region and a second well region on the substrate, wherein the first well region and the second well region have different types of dopants;
• a shallow trench isolation (STI) region on the first well region and the second well region;
• a cell, comprising:
• a first transistor over the first well region;
• and
• a second transistor over the second well region;
• an interlayer dielectric (ILD) layer over the STI region and between the first transistor and the second transistor;
• a VDD line formed in the STI region over the first well region;
• a VSS line formed in the STI region over the second well region;
• a first source/drain contact over and electrically connected to the VDD line and a source region of the first transistor;
• and
• a second source/drain contact over and electrically connected to the VSS line and a source region of the second transistor,
• wherein the first source/drain contact and the second source/drain contact are in direct contact with a top surface of the STI region.

A semiconductor structure, comprising:

• a substrate;
• an N-type well region and a P-type well region on the substrate;
• a shallow trench isolation (STI) region on the N-type well region and the P-type well region;
• a PMOS transistor, comprising:
• first fins formed on the N-type well region;
• and
• P-type doping regions formed on the first fins;
• a NMOS transistor, comprising:
• second fins formed on the P-type well region;
• and
• N-type doping regions formed on the second fins;
• a first power rail over the N-type well region and electrically coupled to VDD;
• a second power rail over the P-type well region and electrically coupled to VSS;
• a first source/drain contact over and electrically connected to the first power rail and the P-type doping regions;
• a second source/drain contact over and electrically connected to the second power rail and the N-type doping regions;
• and
• an interlayer dielectric (ILD) layer over the STI region and between the first transistor and the second transistor,
• wherein the first source/drain contact and the second source/drain contact are vertically in contact with the STI region.