Iii-nitride transistor with top and bottom cap layers with etch stop
AssigneeFinwave Semiconductor, Inc.
InventorsDongfei Pei, Bin Lu
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Abstract
A new transistor structure for use with III-Nitride semiconductor structures is disclosed. This transistor adds a top cap layer, etch stop layer and bottom cap layer between the gate electrode and the barrier layer. This structure enables a fabrication process in which the barrier layer is not subjected to plasma etching, which is a cause of etch related variations. In some embodiments, the bottom cap layer and optionally the etch stop layer extend from the source electrode to the drain electrode. A gate dielectric layer may optionally be included between the gate electrode and the top cap layer.
Claims18
A semiconductor structure for use in a III-Nitride (III-N) semiconductor device, comprising:
- a channel layer;
- a barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer;
- a source electrode and a drain electrode disposed in ohmic contact regions to form an electrical connection to electrons at the interface between the channel layer and the barrier layer;
- a gate electrode disposed between the source electrode and the drain electrode in a gate region;
- a bottom cap layer disposed on the barrier layer;
- an etch stop layer disposed on the bottom cap layer;
- and
- a top cap layer disposed beneath the gate electrode and on the etch stop layer.
A method of fabricating a III-Nitride (III-N) semiconductor device, comprising:
- depositing on a substrate, a buffer layer, a channel layer, a barrier layer, a bottom cap layer, an etch stop layer and a top cap layer, wherein the etch stop layer has a higher aluminum composition than the bottom cap layer and the top cap layer;
- using a mask to remove a portion of the top cap layer, using an etch process that is highly selective to the top cap layer over the etch stop layer;
- removing the mask;
- depositing a dielectric layer over an entirety of the substrate;
- depositing a source electrode and a drain electrode in ohmic contact regions to form an electrical connection to electrons at an interface between the channel layer and the barrier layer;
- removing a portion of the dielectric layer in a gate region;
- and
- depositing a gate electrode on top of the top cap layer in the gate region.
Dependencies are inferred from the claim text.