Integrated circuit device

An integrated circuit device, comprising:

• a substrate including a cell array region and a peripheral circuit region;
• a plurality of active regions defined by an isolation film, the plurality of active regions including a plurality of first active regions in the cell array region and a plurality of second active regions in the peripheral circuit region;
• a word line trench extending longitudinally in a first horizontal direction across the plurality of first active regions, the first horizontal direction extending parallel to a main surface of the substrate;
• a gate dielectric film covering an inner surface of the word line trench;
• a word line on the gate dielectric film, the word line filling a lower space of the word line trench and extending longitudinally in the first horizontal direction;
• an insulating capping pattern on the word line, the insulating capping pattern filling an upper space of the word line trench and extending longitudinally in the first horizontal direction;
• and
• at least one ferroelectric layer at a top portion of the word line, the at least one ferroelectric layer including a first sidewall in contact with the gate dielectric film.

An integrated circuit device, comprising:

• a substrate having formed therein a word line trench, the word line trench extending longitudinally in a first horizontal direction, the first horizontal direction extending parallel to a main surface of the substrate;
• a gate dielectric film covering an inner surface of the word line trench;
• a word line on the gate dielectric film, the word line filling a lower space of the word line trench, the word line extending longitudinally in the first horizontal direction, the word line including a lower conductive plug and an upper conductive plug on the lower conductive plug;
• an insulating capping pattern on the upper conductive plug, the insulating capping pattern filling an upper space of the word line trench and extending longitudinally in the first horizontal direction;
• and
• a ferroelectric layer between the upper conductive plug and the gate dielectric film,
• wherein the ferroelectric layer includes a first ferroelectric layer and a second ferroelectric layer spaced apart from the first ferroelectric layer by a certain distance in a second horizontal direction, the second horizontal direction extending parallel to the main surface of the substrate and perpendicular to the first horizontal direction,
• each of the first ferroelectric layer and the second ferroelectric layer includes a first sidewall and a second sidewall, the first sidewall in contact with the gate dielectric film, the second sidewall opposite to the first sidewall in the second horizontal direction and in contact with the upper conductive plug,
• a top surface of each of the first ferroelectric layer and the second ferroelectric layer is in contact with the insulating capping pattern, and a bottom surface of each of the first ferroelectric layer and the second ferroelectric layer is in contact with the lower conductive plug.